`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    09:38:28 03/17/2014 
// Design Name: 
// Module Name:    rand 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module rand(clk,rand);
	input clk;
	output reg [15:0] rand;
	initial 
		begin
			rand <= 16'h0 ;
		end
	always @(posedge clk)
	begin
		rand[15] <= ~rand[0] ^ rand[1] ^ rand[7] ^ rand[8];
		rand[14] <= rand[15];
		rand[13] <= rand[14];
		rand[12] <= rand[13];
		rand[11] <= rand[12];
		rand[10] <= rand[11];
		rand[9] <= rand[10];
		rand[8] <= rand[9];
		rand[7] <= rand[8];
		rand[6] <= rand[7];
		rand[5] <= rand[6];
		rand[4] <= rand[5];
		rand[3] <= rand[4];
		rand[2] <= rand[3];
		rand[1] <= rand[2];
		rand[0] <= rand[1];
	end
endmodule
